VIP developed as a stack of layered drivers, each layer having an additional control sequencer and customized System Verilog FSM to meet protocol expectations
Highly controllable error injection using
Factory override for layered drivers
Control sequencers for each layer
Object and callback hooks
Advantages over other VIP’s in market
Advanced error injection and literal control of every nook and corner of the protocol
Huge number of Sanity, Complex and Corner case scenarios with functional coverage
Provision for easy integration with RTL
CPORT and RMMI interface level analyzers
IP proven with Functional Qualification methods.
ARM Low Power Interface VIP
Q-Channel and P-Channel Interface
Supports AXI Interconnect Low Power interface
Supports AXI Device Low Power interface
Supports all quiescent states of
Sleep
Domain Reset
Clock gating
Power gating
Supports optional DENY/ACTIVE handshaking
Complex Power State transitions through P-Channel support
Sales
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