DESIGN AND VERIFICATION TOOLS

• Proprietary tool to transform non-LP Design and TB to LP aware
• Automatically generates UPF and CPF with high level specification of power intent
• Makes TB components to drive stimulus understanding DUT power states
• Generates LP checkers and coverage crossed with power states’ active traffic
• CDC signals checkers at DVFS boundaries
• Built-in Power estimation reporting without Gate level netlist
• Generated LP collateral supports all EDA vendors’ tools